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The Resource Microfluidic Very Large Scale Integration (VLSI) : Modeling, Simulation, Testing, Compilation and Physical Synthesis

Microfluidic Very Large Scale Integration (VLSI) : Modeling, Simulation, Testing, Compilation and Physical Synthesis

Label
Microfluidic Very Large Scale Integration (VLSI) : Modeling, Simulation, Testing, Compilation and Physical Synthesis
Title
Microfluidic Very Large Scale Integration (VLSI)
Title remainder
Modeling, Simulation, Testing, Compilation and Physical Synthesis
Creator
Contributor
Subject
Language
eng
Cataloging source
MiAaPQ
Literary form
non fiction
Nature of contents
dictionaries
Microfluidic Very Large Scale Integration (VLSI) : Modeling, Simulation, Testing, Compilation and Physical Synthesis
Label
Microfluidic Very Large Scale Integration (VLSI) : Modeling, Simulation, Testing, Compilation and Physical Synthesis
Link
http://libproxy.rpi.edu/login?url=https://ebookcentral.proquest.com/lib/rpi/detail.action?docID=4398745
Publication
Copyright
Related Contributor
Related Location
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Carrier category
online resource
Carrier category code
cr
Carrier MARC source
rdacarrier
Color
multicolored
Content category
text
Content type code
txt
Content type MARC source
rdacontent
Contents
  • Contents -- Acronyms -- Notations -- 1 Introduction -- 1.1 Microfluidic Biochips -- 1.2 mVLSI Technology -- 1.2.1 Application Areas -- 1.2.2 Motivation for Automated Physical Design and Testing Techniques -- 1.2.3 Motivation for Programming and Control of mVLSI Biochips -- 1.3 Overview -- References -- Part I Preliminaries -- 2 Design Methodology for Flow-Based Microfluidic Biochips -- 2.1 Modeling and Simulation -- 2.2 Physical Design and Testing -- 2.3 Programming and Control -- References -- 3 Biochip Architecture Model -- 3.1 Microfluidic Valve -- 3.2 Component Design -- 3.2.1 Pneumatic Switches -- 3.2.2 Pneumatic Mixer -- 3.3 Illustrative Example -- 3.4 Component Model and Library -- 3.4.1 Component Model -- 3.4.2 Component Model Library -- 3.5 System-Level Architecture Model -- 3.6 On-Chip Control -- 3.6.1 Pneumatic Logical Components -- 3.6.2 Supportive Components -- 3.6.3 Logical Circuits -- 3.6.4 Logic Truth Tables -- References -- 4 Biochemical Application Modeling -- 4.1 High-Level Protocol Language: Aqua -- 4.1.1 Declarations -- 4.1.2 Statements -- 4.2 Biochemical Application Model -- 4.3 Benchmarks -- 4.3.1 Real-Life Benchmarks -- 4.3.2 Synthetic Benchmarks -- References -- Part II Compilation -- 5 Compiling High-Level Languages -- 5.1 Problem Formulation -- 5.2 Application Model Synthesis -- 5.2.1 High-Level Language Grammar -- 5.2.2 Generating the Application Graph -- 5.3 Solving the Mixing Problem -- References -- 6 Application Mapping and Simulation -- 6.1 Application Mapping -- 6.1.1 Problem Formulation -- 6.2 Constraint Programming Strategy -- 6.2.1 Finite Domain Variables -- 6.2.2 Resource Binding Constraints -- 6.2.3 Resource Sharing Constraints -- 6.2.4 Precedence Constraints -- 6.2.5 Cost Function -- 6.3 List Scheduling Strategy -- 6.3.1 Route Generation -- 6.3.2 Optimization -- 6.4 Experimental Evaluation -- 6.5 Simulation
  • References -- 7 Control Synthesis and Pin-Count Minimization -- 7.1 Biochip Control Synthesis -- 7.1.1 Control Logic Generation -- 7.1.2 Pin-Count Minimization -- 7.1.3 Problem Formulation -- 7.2 Synthesis Strategy -- 7.2.1 Control Logic Generation -- 7.2.2 Pin-Count Minimization -- 7.3 Experimental Evaluation -- References -- Part III Physical Design -- 8 Allocation and Schematic Design -- 8.1 Problem Formulation -- 8.2 Allocation and Schematic Design -- 8.2.1 Allocation and Schematic Design -- 8.3 Synthesis Strategy -- 8.3.1 Allocation -- 8.3.2 Schematic Design -- 8.4 Experimental Evaluation -- References -- 9 Placement and Routing -- 9.1 Models, Component Library, and Design Rules -- 9.1.1 Connection Model -- 9.1.2 Grid Graph Model -- 9.1.3 Route Model -- 9.2 Problem Formulation -- 9.2.1 Formalization -- 9.3 Simulated Annealing -- 9.3.1 Concept -- 9.3.2 Implementation -- 9.4 Approximated Cost Function -- 9.4.1 Metrics -- 9.4.2 Computing the Cost Function -- 9.5 Routed Cost Function -- 9.5.1 Routing Algorithms -- 9.5.2 Metrics -- 9.5.3 Computing the Cost Function -- 9.6 Experimental Evaluation -- 9.6.1 Benchmarks -- 9.6.2 Placement Quality -- 9.6.3 Performance -- References -- 10 On-Chip Control Synthesis -- 10.1 Circuit Design -- 10.1.1 Ongoing Example -- 10.1.2 Two-Level Minimization -- 10.1.3 Multiple-Level Optimization -- 10.1.4 Library Binding -- 10.2 Control Synthesis -- 10.2.1 Component Control Logic Generation -- 10.2.2 Routing Control Logic Generation -- 10.3 Physical Synthesis -- 10.3.1 Placement -- 10.3.2 Routing -- 10.4 Evaluation -- 10.5 Benchmarks -- 10.5.1 Evaluation of the Circuit Design -- 10.5.2 Evaluation of the Placement Step -- 10.5.3 Evaluation of the Routing Step -- 10.6 On-Chip and Off-Chip Trade-Off -- 10.7 On-Chip Control Circuits -- References -- 11 Testing and Fault-Tolerant Design -- 11.1 Fault Model and Testing
  • 11.1.1 Fault Model -- 11.1.2 Testing -- 11.1.3 Fault-Tolerant Architecture Synthesis -- 11.1.4 Design Transformations -- 11.1.5 Simulated Annealing -- 11.1.6 GRASP -- 11.1.7 Architecture Evaluation -- 11.2 Experimental Evaluation -- References -- Index
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unknown
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{'f': 'http://opac.lib.rpi.edu/record=b4384856'}
Extent
1 online resource (277 pages)
Form of item
online
Isbn
9783319295992
Media category
computer
Media MARC source
rdamedia
Media type code
c
Sound
unknown sound
Specific material designation
remote

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