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The Resource Design, implementation, and mask verification of a working memory for wafer scale integration implementation of a parallel architecture for a video rate two dimensional FFT processor

Design, implementation, and mask verification of a working memory for wafer scale integration implementation of a parallel architecture for a video rate two dimensional FFT processor

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Design, implementation, and mask verification of a working memory for wafer scale integration implementation of a parallel architecture for a video rate two dimensional FFT processor
Title
Design, implementation, and mask verification of a working memory for wafer scale integration implementation of a parallel architecture for a video rate two dimensional FFT processor
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Dissertation note
Thesis (master's)--Rensselaer Polytechnic Institute, December 1986.
Design, implementation, and mask verification of a working memory for wafer scale integration implementation of a parallel architecture for a video rate two dimensional FFT processor
Label
Design, implementation, and mask verification of a working memory for wafer scale integration implementation of a parallel architecture for a video rate two dimensional FFT processor
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http://library.link/vocab/discovery_link
{'f': 'http://opac.lib.rpi.edu/record=b1173806'}
Extent
184 p.

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