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The Resource Correct hardware design and verification methods : IFIP WG 10.5 advanced research working conference, CHARME '95, Frankfurt/Main, Germany, October 2-4, 1995 : proceedings, Paolo E. Camurati, Hans Eveking (eds.)

Correct hardware design and verification methods : IFIP WG 10.5 advanced research working conference, CHARME '95, Frankfurt/Main, Germany, October 2-4, 1995 : proceedings, Paolo E. Camurati, Hans Eveking (eds.)

Label
Correct hardware design and verification methods : IFIP WG 10.5 advanced research working conference, CHARME '95, Frankfurt/Main, Germany, October 2-4, 1995 : proceedings
Title
Correct hardware design and verification methods
Title remainder
IFIP WG 10.5 advanced research working conference, CHARME '95, Frankfurt/Main, Germany, October 2-4, 1995 : proceedings
Statement of responsibility
Paolo E. Camurati, Hans Eveking (eds.)
Title variation
CHARME '95
Creator
Contributor
Subject
Genre
Language
eng
Member of
Cataloging source
DLC
Illustrations
illustrations
Index
no index present
LC call number
TK7874.75
LC item number
.A39 1995
Literary form
non fiction
Nature of contents
bibliography
Series statement
Lecture notes in computer science
Series volume
987
Correct hardware design and verification methods : IFIP WG 10.5 advanced research working conference, CHARME '95, Frankfurt/Main, Germany, October 2-4, 1995 : proceedings, Paolo E. Camurati, Hans Eveking (eds.)
Label
Correct hardware design and verification methods : IFIP WG 10.5 advanced research working conference, CHARME '95, Frankfurt/Main, Germany, October 2-4, 1995 : proceedings, Paolo E. Camurati, Hans Eveking (eds.)
Publication
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Bibliography note
Includes bibliographical references
Contents
What if model checking must be truly symbolic / H. Hungar ... [et al.] -- Automatic verification of the SCI cache coherence protocol / U. stern, D.L. Dill -- Describing and verifying synchronous circuits with the Boyer-Moore theorem prover / L. Pierre -- Problems encountered in the machine-assisted proof of hardware / P. Curzon -- Formally embedding existing high level synthesis algorithms / D. Eisenbiegler, R. Kumar -- Formal design of a class of computers / L.G. Wang, M. Mendler -- Symbolic analysis and verification of CPA descriptions / M.C. McFarland, T.J. Kowalski -- A foundation for formal reuse of hardware / A.C.V. de Melo, H. Barringer -- State enumeration with abstract descriptions of state machines / F. Corella ... [et al.] -- Transforming boolean relations by symbolic encoding / G. Cabodi ... [et al.] -- Design error diagnosis in sequential circuits / A. Wahba, D. Borrione -- Timing analysis of asynchronous circuits using timed automata / O. Maler, A. Pnueli -- Improved probabilistic verification by hash compaction / U. Stern, D.L. Dill -- Formal support for the ELLA hardware description language / H. Barringer, B. Monahan, A. Williams -- Verifying hardware components within JACK / R. De Nicola ... [et al.] -- Language containment of non-deterministic [omega]-automata / S. Taşiran, R. Hojati, R.K. Brayton -- A partial-order approach to the verification of concurrent systems : checking liveness properties / D. Bolignano -- Semantics of a verification-oriented subset of VHDL / D. Déharbe, D. Borrione -- Reasoning about VHDL using operational and observational semantics / K.G.W. Gossens -- A symbolic relation for a subset of VHDL '87 descriptions and its application to symbolic model checking / E. Encrenaz
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https://contentcafe2.btol.com/ContentCafe/Jacket.aspx?Return=1&Type=S&Value=9783540603856&userID=ebsco-test&password=ebsco-test
Dimensions
24 cm.
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{'f': 'http://opac.lib.rpi.edu/record=b1321656'}
Extent
viii, 342 p.
Isbn
9783540603856
Isbn Type
(acid-free paper)
Lccn
95039591
Other physical details
ill.

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