Coverart for item
The Resource Co-verification of hardware and software for ARM SoC design, by Jason R. Andrews

Co-verification of hardware and software for ARM SoC design, by Jason R. Andrews

Label
Co-verification of hardware and software for ARM SoC design
Title
Co-verification of hardware and software for ARM SoC design
Statement of responsibility
by Jason R. Andrews
Creator
Subject
Language
eng
Summary
Hardware/software co-verification is how to make sure that embedded system software works correctly with the hardware, and that the hardware has been properly designed to run the software successfully -before large sums are spent on prototypes or manufacturing. This is the first book to apply this verification technique to the rapidly growing field of embedded systems-on-a-chip(SoC). As traditional embedded system design evolves into single-chip design, embedded engineers must be armed with the necessary information to make educated decisions about which tools and methodology to deploy. SoC verification requires a mix of expertise from the disciplines of microprocessor and computer architecture, logic design and simulation, and C and Assembly language embedded software. Until now, the relevant information on how it all fits together has not been available. Andrews, a recognized expert, provides in-depth information about how co-verification really works, how to be successful using it, and pitfalls to avoid. He illustrates these concepts using concrete examples with the ARM core - a technology that has the dominant market share in embedded system product design. The companion CD-ROM contains all source code used in the design examples, a searchable e-book version, and useful design tools. * The only book on verification for systems-on-a-chip (SoC) on the market * Will save engineers and their companies time and money by showing them how to speed up the testing process, while still avoiding costly mistakes * Design examples use the ARM core, the dominant technology in SoC, and all the source code is included on the accompanying CD-Rom, so engineers can easily use it in their own designs
Member of
Cataloging source
OPELS
Illustrations
illustrations
Index
index present
Literary form
non fiction
Nature of contents
dictionaries
Series statement
Embedded technology series
Co-verification of hardware and software for ARM SoC design, by Jason R. Andrews
Label
Co-verification of hardware and software for ARM SoC design, by Jason R. Andrews
Link
http://libproxy.rpi.edu/login?url=http://www.sciencedirect.com/science/book/9780750677301
Publication
Note
Includes index
Related Contributor
Related Location
Related Agents
Related Authorities
Related Subjects
Related Items
Carrier category
online resource
Carrier category code
cr
Carrier MARC source
rdacarrier
Color
multicolored
Content category
text
Content type code
txt
Content type MARC source
rdacontent
Contents
1. Embedded System Verification -- 2. Hardware and Software Design Process: System initialization software and hardware abstraction layer (HAL), Hardware diagnostic test suite, Real-time operating system (RTOS), RTOS device drivers, Application software, C simulation, Logic simulation, Simulation acceleration, Emulation, Prototype; -- 3. SoC Verification Topics for the ARM Architecture; -- 4. Hardware/Software Co-Verification: Host-code execution -- implicit access, ISS + BIM, CCM, RTL, Hardware model, Emulation board, FPGA Prototype; -- 5. Advanced Hardware/Software Co-Verification: Direct access to simulation memories without advancing simulation time, Memory and time optimizations -- understanding synchronization, Cross network connections versus using a single workstation, C modeling for some of the hardware, Implicit Access, Post-processing techniques for software debugging, Synchronized software and hardware views for debugging, Post-processing software trace, Save/restore, How to deal with peripherals, How to deal with an RTOS; -- 6. Hardware Verification Environment and -- Co-Verification: Testbench, The use of testbench tools, Random test generation based on CPU address map, CPU bus protocol checking, Functional/ Transaction coverage, Memory coverage, Property checking -- did a specific scenario ever happen? Use of a design signoff model; -- 7. Methodology for an Example ARM SoC
http://library.link/vocab/cover_art
https://contentcafe2.btol.com/ContentCafe/Jacket.aspx?Return=1&Type=S&Value=9780080476902&userID=ebsco-test&password=ebsco-test
Dimensions
unknown
http://library.link/vocab/discovery_link
{'f': 'http://opac.lib.rpi.edu/record=b4170138'}
Extent
1 online resource (xxiii, 260 pages)
Form of item
online
Isbn
9780080476902
Media category
computer
Media MARC source
rdamedia
Media type code
c
Other physical details
illustrations.
Specific material designation
remote

Library Locations

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      42.729766 -73.682577
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